1. Field of the Invention
This invention relates to a field emission cathode device known as a cold cathode device, and more particularly to an improvement in a field emission cathode device.
2. Discussion of the Background
Application of an electric field of the order of about 10.sup.9 V/m to a surface of a metal material or a semiconductor material leads to a tunnel effect, to thereby permit electrons to pass through a barrier. This results in the electrons being discharged to a vacuum even at a normal temperature. Such a phenomenon is generally referred to as "field emission" and a cathode constructed so as to emit electrons based on such a principle is referred to as "field emission cathode" (hereinafter also referred to as "FEC").
Recently, semiconductor integration techniques permit an FEC of a size as small as microns to be produced.
Now, manufacturing of an FEC of the Spindt type which is an example of such a small-sized FEC by the semiconductor integration techniques will be described hereinafter with reference to FIGS. 5(a) to 5(f).
First, as shown in FIG. 5(a), a substrate 101 made of glass or the like is formed thereon with a cathode conductor 102, a resistive layer 103, an insulating layer or SiO.sub.2 layer 104 and a gate conductor 105 by vapor deposition or the like in order. The cathode conductor 102 comprises a metal layer, the resistive layer 103 is formed of amorphous silicon or the like, the insulating layer 104 is made by subjecting silicon to thermal oxidation, and the gate conductor 105 comprises a metal layer of Nb or the like.
Then, the gate conductor 105 is coated thereon with a resist layer 106, followed by patterning as shown in FIG. 5(b). Subsequently, etching is carried out, resulting in an aperture 107 being formed through both the gate conductor 105 and insulating layer 104, followed by removal of the resist layer 106, as shown in FIG. 5(c).
Thereafter, a peel layer 109 is formed on the gate conductor 105 by depositing aluminum in a direction oblique to the substrate 101 while rotating the substrate 101. This permits the peel layer 109 to be formed on only a surface of the gate conductor 105 while being prevented from being formed in the aperture 107, as shown in FIG. 5(d). Then, deposition of Mo is carried out, resulting in a deposit layer 110 being formed on the peel layer 109 and an emitter deposit layer 111 of a conical shape being formed in the aperture 107, as shown in FIG. 5(e). Finally, the peel layer 109 and deposit layer 110 on the gate conductor 105 are removed by etching, so that an FEC may be provided as shown in FIG. 5(f).
Manufacturing of the FEC of FIG. 5(f) by the semiconductor integration techniques carried out as described above permits a distance between the conical emitter 111 and the gate conductor 105 to be defined to be as small as submicrons, so that application of a voltage of tens of volts between the emitter 111 and the gate conductor 105 may lead to emission of electrons from the emitter 111.
Such a construction of the FEC as shown in FIG. 5(f) permits FECs in number as many as tens of thousands to hundreds of thousands to be provided on a single substrate because a distance between each adjacent two emitters 111 may be defined to be as small as 5 to 10 microns.
This permits an FEC device of the surface discharge type in which a number of the FECs are incorporated to be manufactured, thus, it is proposed to apply it to a fluorescent display device, a CRT, an electron microscope, an electron beam device and the like.
Now, such an FEC device of the surface discharge type will be described hereinafter with reference to FIG. 6.
The FEC device includes a substrate 101, which is formed thereon with a cathode conductor 102. The cathode conductor 102 is then formed thereon with a resistive layer 103, on which emitters 111 each formed into a conical shape are provided. Also, the cathode conductor 102 is formed thereon with a gate conductor 105 through an insulating layer 104. The gate conductor 105 and insulating layer 104 are commonly formed with apertures 107 of a round shape so as to extend therethrough, through which the conical emitters 111 are exposed at a distal end thereof.
In the FEC device of the surface discharge type thus constructed, application of a driving voltage of tens of volts between the gate conductor 105 and the cathode conductor 102 permits each of the emitters 111 to emit electrons, which are then captured by an anode conductor 112 which is arranged so as to be upwardly spaced therefrom and to which an anode voltage V.sub.A is applied. Thus, when phosphors are arranged on the anode conductor 112, electrons captured by the anode conductor 112 permit the phosphors to emit light. The FEC device is so constructed that electrons travel in a space, thus, operation of the FEC device is carried out in a vacuum atmosphere.
Now, the reason why the resistive layer 103 is arranged between the emitters 111 and the cathode conductor 102 will be described hereinafter.
In general, each of the FECs of the FEC device is so constructed that a distance between the distal end of each of the conical emitters and the gate conductor is defined to be as small as submicrons and tens of thousands to hundreds of thousands of emitters are provided on the single substrate. Unfortunately, such a construction causes short-circuiting between any of the emitters and the gate conductor due to entrance of dust or the line into the FEC. Even when such short-circuiting occurs on only one emitter, short-circuiting is caused between the cathode conductor and the gate conductor, to thereby cause a failure in application of a voltage to all the emitters, leading to a failure in operation of the whole FEC device.
Also, the conventional FEC device often meets with a disadvantage that entrance of any gas into the device often occurs at an initial stage of operation of the FEC device, to thereby cause discharge between any of the emitters and the gate conductor or anode conductor, so that a large amount of current flows to the cathode conductor, leading to breakage of the cathode conductor.
Also, of a number of emitters, a part tends to readily emit electrons as compared with the remaining part. This results in electrons being concentratedly emitted from the part of the emitters, resulting in luminance on an image plane being non-uniform.
In view of the foregoing, it is considered that the resistive layer 103 is arranged between the cathode conductor 102 and the emitters 111 as shown in FIGS. 5(a) to 5(f) and FIG. 6. In such an arrangement, the resistive layer 103 leads to a voltage drop between the gate conductor 105 and the cathode conductor 102 when short-circuiting occurs between the emitters 111 and the gate conductor 105. A voltage due to the voltage drop is applied between a portion of the gate conductor 105 and that of the cathode conductor 102 at which emitters free from short-circuiting are arranged, so that the emitters free from short-circuiting may emit electrons. Further, the resistive layer 103 restrains a short-circuit current from flowing to the cathode conductor 102, to thereby prevent breakage of the cathode conductor 102.
Also, when a current is caused to concentratedly flow through any of the emitters as described above, the resistive layer 103 leads to a voltage drop of a significant magnitude across the emitter, so that a potential across the emitter is increased, resulting in a decrease in voltage between the portion of the gate conductor and that of the cathode conductor described above. This permits the emitter current to be reduced, to thereby prevent concentration of the emitter current.
Thus, it will be noted that arrangement of the resistive layer 103 improves yields in manufacturing of the FEC device and ensures stable operation of the FEC device.
In the conventional FEC device, the resistive layer 103 is arranged all over the substrate 101 as shown in FIG. 6. Unfortunately, such an arrangement of the resistive layer 103 causes operation of the emitters in a manner to be independent from each other to be highly difficult, resulting in cross-talk often occurring. The cross-talk leads to leakage luminance in a display device in which the FEC device is incorporated.
In view of the problem, it is proposed that an FEC device is constructed so as to permit emitters to be operated independent from each other when the short-circuiting occurs, as shown in FIG. 7. Such a proposal is disclosed in Japanese Patent Application Laid-Open Publication No. 284324/1992.
The FEC device proposed, as shown in FIG. 7, includes a silicon substrate 120, on which an insulating layer 121 is formed. The insulating layer 121 is provided thereon with a plurality of gate conductors 122 each formed at a central portion thereof with an aperture 123. The gate conductors 122 are connected through fusible resistance elements 126 of a reduced width to a common gate line 125, respectively. The apertures 123 each are formed therein with an emitter 124 of a conical shape.
In the FEC device thus constructed, when short-circuiting occurs between any of the emitters 124 and the gate electrode 122, a short-circuit current flows through the fusible resistance elements 126 of the emitter, to thereby cause Joule heat to be generated in the fusible resistance elements 126, resulting in the fusible resistance element 126 being instantaneously broken due to fusing. Thus, the gate conductor 122 short-circuited is separated from the gate line 125 serving as a feed line, to thereby be interrupted, whereas the remaining FECs free from short-circuiting are properly fed with electricity, resulting in carrying out normal operation.
Unfortunately, the FEC device of FIG. 7 exhibits a disadvantage that fusing of the fusible resistance element 126 causes a material of the element fused to scatter and travel to the normal FECs, to thereby enter into an aperture of each of the FECs, leading to additional short-circuiting.
Another disadvantage encountered with the FEC device is that it is highly difficult to form the fusible resistance element 126 of a width as small as submicrons for every gate conductor because a distance between the emitter and the gate conductor 112 is defined to be as small as submicrons, resulting in the fusible resistance element being often broken during manufacturing of the device.